One type of semiconductor memory device uses two different dielectric materials forming layers in the channel region of the device to form a charge storage center. The interfacial region between the two different dielectric materials forms an electron trapping region that creates the charge storage center. Such devices are often referred to as MIOS (metal insulator oxide semiconductor) devices. Where the insulator material is silicon nitride such devices are commonly referred to as MNOS devices. Such devices and their properties are well known in the art (e.g., see S. M. Sze, Physics of Semiconductor Devices (John Wiley & Sons, New York, 2nd Ed., 1981) Section 8.6.2).
One example of a conventional prior art MIOS memory device is described hereinbelow. In FIG. 1 a portion of typical MIOS memory cell 10 is depicted. A semiconductor substrate 100 (e.g., a p-doped silicon wafer) includes a “channel” region 101 positioned between a source 102 and a drain 103 (e.g., n-doped regions). A first dielectric layer 104 (e.g., silicon dioxide) is formed on the substrate surface. Commonly polysilicon electrodes 105, 106 are formed on the first dielectric layer 104. A second layer of dielectric material 107 is formed over the first dielectric layer 104 and portions of the polysilicon electrodes 105, 106 in the channel region 101. A gate electrode 108 is formed over the second dielectric layer 107. In the interests of simplifying the discussion, the remaining portions of the memory cell 10 are not depicted.
In conventional MIOS memory cells, the first dielectric layer 104 is formed of silicon dioxide and the second dielectric layer 107 is formed of, for example, silicon oxynitride. The interfacial region between the first dielectric layer 104 and the second dielectric layer 107 creates an interfacial charge storage layer 109 which can, among other things, be used to alter the amount of voltage required to change the memory state of the cell. Such devices are relatively small, resistant to ionizing radiation, and can alter the write and erase times (and voltages).
However, such memory structures also suffer from some drawbacks. One drawback is that the interfacial charge storage layer 109 between the first dielectric layer 104 and the second dielectric layer 107 is difficult to form reproducibly and reliably. Additionally, interfacial charge storage layers 109 formed in this manner suffer from unpredictable electron trapping properties, further adding to their unpredictability and reliability problems. This inability to reliably and reproducibly fabricate interfacial charge storage layers leads to unpredictable and inconsistent behavior in such memory structures. Additionally, it is difficult to vary the amount of charge stored by the interfacial charge storage layer 109 or to alter the strength of an electron trapping environment. Thus, such devices are not particularly flexible in their application. Moreover, as feature sizes decrease these problems become aggravated and also more difficult to solve. These problems become particularly intractable as feature sizes decrease below the 0.1 micron (μ) level.
Although suitable for many purposes, conventional MIOS and MNOS memory structures suffer from many difficulties. The principles of the present invention are directed toward improved memory structures and improved methodologies for constructing such memory structures.